ECE 520.222
Computer Architecture (3 credits)
For Spring 2014, meeting room Barton 117, Tues/Thurs 3:00-4:15 PM

Instructor: Robert Jenkins, Senior Lecturer, ECE
Office: 206 Barton Hall
Telephone: (410) 516-7380
Office Hours: Barton 123 or Barton 206, Thursdays after class

Spring 2015 TA: Mr. Mael Illian
Office Hours: TBA

Updated 1/26/2015.

Course Description

An introductory course in computer architecture methods, with the material limited to single processor systems.

What you will NOT learn in this class: The class is not intended to describe the detailed hardware in modern information processing systems like the latest smart phones, ARM, x86, Laptops, or Workstations. Rather, the class intent is to put the student in a position to understand and absorb literature about the specifics of such modern computing hardware.

What you WILL learn in the class: General architectural methods and their historical evolution, alternative approaches, trade-offs, models for computer hardware design and performance estimation, what's going on inside a CPU, and possible ways to organize memory systems.

Topics include: a history of modern machines starting from the Turing model of computing, instruction sets, addressing, RISC versus CISC, traps and interrupt handling, twos complement arithmetic, adders and ALUs, multiplication, control unit design, micro-programming, instruction pipelining, performance estimation, static and dynamic linking methods, memory systems and memory management - paging, segmentation, possible cache organizations and replacement policies.

The course emphasizes hardware rather than software, and uses Tanenbaum's hierarchical, multi-level model of a computer system. A good deal of discussion is aimed at understanding how computer features and CPU control are implemented via finite state logic, buses and registers, control signals, and ROM. The course is intended to provide a hardware background for advanced information processing courses and labs in ECE.

Back to top


520.142, Digital Systems Fundamentals.
Basic knowledge of computers. Some knowledge of assembly language helpful, but not required.

Textbook and other class material

 1. Tanenbaum, Structured Computer Organization , Prentice-Hall, 
	a used 4th edition or later will be OK.

 2. Handout class notes describing the detailed covered material. 
	The text supplements the class notes, and contains detailed 
	material used in some parts of the class.

 3. Classic published papers from the literature as reference material, e.g.-
	D. Patterson and C. Sequin, "A VLSI RISC", IEEE Computer, 1983.

	D. Fairclough et al, "A Unique Microprocessor Instruction Set", IEEE Micro, 1982.

	J. Hennessy, "VLSI RISC Processors", VLSI Systems Design, 1985.

	Smith, "Cache Memory Design: an Evolving Art", IEEE Spectrum, 1989.

Back to top

Course Objectives

1. provide a grounding in the architecture of classical von Neuman computers, including knowledge of the historical roots and evolution of modern methods, and why things evolved as they did.

2. create an understanding of the trade-offs involved in computing hardware, along with an understanding of the methods used to evaluate performance and obtain the data needed for trade studies.

3. give design experience through problems involving architectural decisions.

4. provide an introductory background for more advanced studies of computer and information processing systems.

5. prepare students to be able to read and understand current literature in computer architecture.

Back to top

Course Syllabus

Week1 - Hierarchical models of computers, virtual machines and interpreters, the Turing model of computing, Turing machines and universal Turing machines with analogy to virtual machines, Turing machine examples.

Week2 - Early development of modern Von Neuman machines, the IAS machine, review of early developments in decades after IAS, the PDP-11 as a model for modern microprocessors with bus type architectures and memory mapped IO

Week3 - Instruction set design, expanding opcodes, register-level descriptions of instructions, addressing modes, PDP-11 instruction set, stacks, use of stacks in argument passing and dynamic storage, traps and interrupt handling.

Week 4 - Instruction set usage, RISC philosophy, RISC vs CISC, discussion of early RISC architecture.

Week 5 - Hardware for 2's complement binary arithmetic, adders, carry look-ahead, floating point, ALU's.

Week 6 - Hardware for 2's complement multiplication and division, Booth's algorithm, modified Booth's algorithm, CSA trees, introduction to CPU data control, internal CPU buses, register tri-stating, control signals and clock phasing.

Week 7 - midterm exam and discussion.

Week 8 - control unit design, introduction to micro-programming and microstore, CPU Performance-CPI and MIPS, the Virtual JAVA Machine

Week 9 - Tanenbaum's Mic-1 micro-architecture, discussion of the microprogram for a Virtual JAVA Machine, take-home micro-programming problems assigned, trade-offs at the micro-architecture level.

Week 10 - Horizontal versus vertical microcoding, Nanoprogramming versus microprogramming. Further discussion of the Mic-2, -3, and -4, overlapped micro-ops and pipelining, handling interrupts at microprogram level, RISC re-visited from a control point of view, RISC instruction pipelining, the picoJava II cpu.

Week 11 - Compiling, linking, and loading, Static and dynamic linking/loading, dynamic link libraries in Windows systems, introduction to memory systems.

Week 12 - Virtual memory and the RAM/Disk hierarchy, principle of locality revisited, hit ratios, access speed vs storage tradeoff, paging vs. segmentation, replacement strategies.

Week 13 - Cache, cache mapping schemes, replacement strategies, write-through, write-back, read-through, cache management and directory hardware.

Week 14 - Final exam.

Back to top


Two Exams, Midterm and Final, each worth 100 points toward final grade.

Approx. 11 homework assignments, worth 100 total points. Weekly homework assignments are due the following week, and will be gone over in class.

There may be an in-class or take-home problem that would be worth around 30 points.


As an Engineering student at this University you carry the obligation to uphold the highest standard of academic and professional integrity. For this class, you are expected to follow the general University guidelines regarding ethical behavior. Unless given specific instructions to the contrary, it is not permitted to collaborate with other students in the class when solving homework or graded take-home projects. It is not permitted, under any circumstances, to consult or plagiarize past homework or take-home design problems. Cheating during an exam is considered a serious violation of ethical integrity. Academic misconduct will be reported to the University's academic ethics board for further consideration. For more information, please refer to the following material:

The Johns Hopkins University Undergraduate and Graduate Programs Catalogue.

The Johns Hopkins University Undergraduate Advising Manual.

Back to top