Laboratory Assignments
Lab #1: The age of exponential scaling. Due: February 15th.
Here is a tutorial on how to find articles with IEEE Explore!
Lab #2: Introduction to CAD tools for physical and logical design. Due: March 8th.
Check the FAQ page (item 4) for help on running the windows CAD software under Mac OSX or Linux. Both microwind2 and dsch2 are tested and they work fine under Codeweavers Crossover for Mac OSX. They run reliably in a windows XP bottle. Since there is no installer for these programs, just unzip the VLSI_CADTools2011.zip file and put the unzipped file somewhere on your disk. Then from the Programs Crossover drop down menu select "Run Command" with an XP bottle selection and browse to the executable you want to run. Create a menu shortcut if you like.
When you download password protected pdf and zip files under Mac OSX, sometimes the file will fail to open upon clicking on it. Download the file instead on the desktop and open it there, do not open directly from the browser window.
Lab #3: Sequential CMOS circuits; design and simulation of a digital clock. Due: March 15th.
Lab #4: CMOS Arithmetic Logic Unit; design, simulation and optimization of a simple calculator. Due: March 29th.
Final Project
The final project will be the design of a computer architecture for image processing! More specifically we will re-create in modern silicon CMOS technology the CLIP processor architecture discussed in Lecture 18 (please also see reading assignment in Week 12).
We will use APRON simulation environment to explore various architectural tradeoffs.You will find instructions on how to instal the environment on your computer here.
Part I: Exploration and learning of the the APRON simulation environment. Due: April 26th.
Part II: CLIP-JHU architecture simulation; design and simulation of a small CMOS CLIP-JHU array: Due: May 5th.
Part III: Final project report. Due: 5:01 p.m. May 18th.
As an optional extra credit goal, the students can also implement a high level programming language to facilitate the programming of the processor. The hierarchical logic formalism in the two papers below may be useful as you design the high level programming language.
Tanimoto. A hierarchical cellular logic for pyramid computers. Journal of Parallel and Distributed Computing (1984) vol. 1 (2) pp. 105-132 (pdf)
Pfeiffer. HCL -A language for level image analysis. Journal Of Parallel And Distributed Computing (1990) vol. 8 (3) pp. 231-244 (pdf)