Lecture Notes and Tutorial Problem Sets
Week 1 (2/1)
Handout 1. Introduction to VLSI systems (pdf); Handout 2. Basics of information and information processing (pdf)
Reading Assignments: Cramming more components onto integrated circuits (G. Moore 1965), Science in an Exponential World (Szalay and Gray 2006). A good introduction to the course can also be found in Sicard/Delmas-Bendhia Chapter 1, Sections 1.1 to 1.7
Tutorial problems: Problem set 1 (pdf) and solutions 1 (pdf)
Week 2 (2/8)
Handout 3. The digital abstraction, voltage based encoding, noise and noise margins (pdf)
Tutorial problems: Problem set 2 (pdf) and solutions 2 (pdf)
Week 3 (2/15)
Handout 4. Combinational logic (pdf); Handout 5. CMOS fabrication
Reading assignment: CMOS fabrication is discussed in Sicard/Delmas-Bendhia Chapter 2, Sections 2.1 to 2.4. The basic structure of a CMOS gate (NAND gate) is discussed in Chapter 6, Sections 6.1, 6.2, 6.3, 6.4.1, 6.4.
Tutorial problems: Problem set 3 (pdf) and solutions 3 (pdf)
Week 4 (2/22)
Handout 6. NMOS, CMOS and combinational logic circuits (pdf); Handout 7. Sequential Logic (pdf)
Reading assignment: The abstraction of an MOS transistor is discused in Sicard/Delmas-Bendhia Chapter 2, Sections 2.5. 2.8 and 2.9. The basis of sequential logic circuits are discussed in Sicard/Delmas-Bendhia Chapter 8, sections 8.1 to 8.4.
Tutorial problems: Problem set 4 (pdf) and solutions 4 (pdf); Tutorial problems: Problem set 5 (pdf) and solutions 5 (pdf)
Week 5 (3/1, Quiz 1: Tutorial sets 1-4)
Handout 8. Finite State Machines, synchronization, metastability (pdf)
Reading assignment: Finite state machines in Ward and Halstead Chapter 6; Applications of sequential logic in counters and dividers in Sicard/Delmas-Bendhia Chapter 8, Section 8.5 to 8.7; Finite State Machines handout (pdf)
Tutorial problems: Problem set 6 (pdf) and solutions 6 (pdf); Tutorial problems: Problem set 7 (pdf) and solutions 7 (pdf)
Week 6 (3/8)
Handout 9. Storage hierarchy, performance and costs (pdf); Handout 10. Parallel processing, pipelining, Amdahl's law (pdf)
Reading assignment: Cassidy and Andreou, Beyond Amdahl's law: An objective function that links multiprocessor performance gains to delay and energy. IEEE Transactions on Computers (pdf)
Tutorial problems: Problem set 8 (pdf) and solutions 8 (pdf)
Week 7 (3/17, Quiz 2: Tutorial sets 5-8)
Handout 11. Introduction to asynchronous circuits (pdf); Handout 12. Asynchronous circuit synthesis (pdf)
Tutorial problems: Problem set 9 (pdf) and solutions 9 (pdf)
Spring Break
Week 8 (3/29)
Handout 13. Optimization in VLSI design: sizing transistors for optimum delay and energy (pdf); Handout 14. Interconnect technologies (pdf)
Reading assignment: Benini and De Micheli. Networks on chips: a new System On Chip (SOC) paradigm. Computer (2002) vol. 35 (1) pp. 70 - 78 (pdf)
Week 9 (4/5)
Handout 15. Programmability and modesl of computation (pdf); Handout 16. General purpose processor instruction set design (pdf)
Reading assignment: Interpretation in Ward and Halstead Chapter 10; Models of computation handout (pdf)
Week 10 (4/12)
Handout 17. Simple processor design (pdf); Handout 18. Parallel processing: Single Instruction Multiple Data (SIMD) architecture (pdf)
Reading assignment: Architectural horizons Ward and Halstead Chapter 21; Processor taxonomy handout (pdf)
Flynn. Some Computer Organizations and Their Effectiveness. IEEE Transactions on Computers (1972) vol. C-21 (9) pp. 948 - 960 (pdf)
Kapasi et al. Programmable stream processors. Computer (2003) vol. 36 (8) pp. 54 - 62 (pdf)
Week 11 (4/19)
Handout 19. Emerging models of computation I: Bio-inspired architectures (pdf); Handout 20. Emerging models of computation II (pdf)
Week 12 (4/26)
In class CLIP processor architecture and project discussion (with Teaching Assistant)
Reading assignment: Duff et. al. A cellular logic array for image processing. Pattern Recognition (1973) vol. 5 (3) pp. 229-247 (pdf)
Note: Thomas Murray, the T.A. has pointed out that there is a few typos/errors in the paper by Duff et. al 1973. Here is a list:
1) In fig. 2, the negated input OR gates should be NOR gates in order for the labeled logic to match the schematic.
2) In fig. 3, the A1' signal is inverted relative to the same signal labeled in fig 2.
3) In fig. 3, the neighbor inputs are passed through an OR gate, while in fig. 2, they are passed through a NAND gate.
Duff and Watson. The cellular logic array processor. The Computer Journal (1975) vol. 20 (1) pp. 68-71 (pdf)
Week 13 (5/3)
Project discussion and project progress report (Tuesday); Project class presentation (Thursday)