Laboratory Assignments
Lab #1: The age of exponential scaling. Due: February 14th.
Here is a tutorial on how to find articles with IEEE Explore!
Lab #2: CAD tools for physical and logical design and simulation (I). Due: February 23rd.
Check the FAQ page (item 4) for help on running the windows CAD software under Mac OSX or Linux. Both microwind2 and dsch2 are tested and they work fine under Codeweavers Crossover for Mac OSX. They run reliably in a windows XP bottle. Since there is no installer for these programs, just unzip the VLSI_CADTools2011.zip file and put the unzipped file somewhere on your disk. Then from the Programs Crossover drop down menu select "Run Command" with an XP bottle selection and browse to the executable you want to run. Create a menu shortcut if you like. When you download password protected pdf and zip files under Mac OSX, sometimes the file will fail to open upon clicking on it. Download the file instead on the desktop and open it there, do not open directly from the browser window.
Lab #3: Sequential CMOS circuits; design and simulation of a digital clock. Due: March 15th.
Final Project
Part #1: Physical layout of an ultra-low voltage cell library. Work by yourself; you can collaborate and discuss the project with your classmates but you need to submit your own design and report. Due: April 19th.
Download and read the following:
[1] N. Lotze and Y. Manoli, “A 62 mV 0.13um {CMOS} Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic,” IEEE Journal of Solid State Circuits, vol. 47, no. 1, pp. 47–60, 2012. (pdf)
[2] J.D. Djigbenou and D.S. Ha, "Development and distribution of 0.25um TSMC standard CMOS Library Cells," 2007 International Symposium on Microsystems Education. (pdf)
Part #2: Functional blocks for an ultra-low voltage neuromorphic processor. Work in groups as instructed in the writeup; collaborate and discuss the project with your classmates. Submit a report as a group. Design and final report due: May 16th.(in lieu of final examination).
Download and read the following:
[1] J. Seo, B. Brezzo, Y. Liu, B. D. Parker, S. K. Esser, R. K. Montoye, B. Rajendran, J. A. Tierno, L. Chang, and D. S. Modha, “A 45nm {CMOS} neuromorphic chip with a scalable architecture for learning in networks of spiking neurons,” 2011 IEEE Custom Integrated Circuits Conference, (CICC 2011), pp. 1–4, 2011. (pdf)
[2] A. Wang and A. Chandrakasan, “A 180-mV subthreshold {FFT} processor using a minimum energy design methodology,” IEEE Journal of Solid State Circuits, vol. 40, no. 1, pp. 310–319, 2005. (pdf)